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authoredgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-05 17:17:55 +0000
committeredgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-05 17:17:55 +0000
commit980f8a0b394b8542e49a8df0db420e9862b8f3d1 (patch)
tree8dfeb910bd2ca1b9f1d11302a19d362f281e572c /target-cris/helper.c
parent00dbbb03b6cc818f1791577236fbe855e94ec1cd (diff)
downloadqemu-980f8a0b394b8542e49a8df0db420e9862b8f3d1.tar.gz
CRIS: Mask off the cache selection bit after MMU translations.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5170 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-cris/helper.c')
-rw-r--r--target-cris/helper.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/target-cris/helper.c b/target-cris/helper.c
index a869ee154e..4f5ffba1ec 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -89,7 +89,11 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
}
else
{
- phy = res.phy;
+ /*
+ * Mask off the cache selection bit. The ETRAX busses do not
+ * see the top bit.
+ */
+ phy = res.phy & ~0x80000000;
prot = res.prot;
r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu);
}