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authorAnthony Liguori <aliguori@amazon.com>2014-01-24 15:52:44 -0800
committerAnthony Liguori <aliguori@amazon.com>2014-01-24 15:52:44 -0800
commit0169c511554cb0014a00290b0d3d26c31a49818f (patch)
tree14a38b1ffe2fde4125b57198698c5ba791feea58 /target-i386/cpu.h
parent1c51e68b182bb335464bb19ad2517fd43c58c127 (diff)
parent439d19f2922ac409ee224bc1e5522cee7009d829 (diff)
downloadqemu-0169c511554cb0014a00290b0d3d26c31a49818f.tar.gz
Merge remote-tracking branch 'qemu-kvm/uq/master' into staging
* qemu-kvm/uq/master: kvm: always update the MPX model specific register KVM: fix addr type for KVM_IOEVENTFD KVM: Retry KVM_CREATE_VM on EINTR mempath prefault: fix off-by-one error kvm: x86: Separately write feature control MSR on reset roms: Flush icache when writing roms to guest memory target-i386: clear guest TSC on reset target-i386: do not special case TSC writeback target-i386: Intel MPX Conflicts: exec.c aliguori: fix trivial merge conflict in exec.c Signed-off-by: Anthony Liguori <aliguori@amazon.com>
Diffstat (limited to 'target-i386/cpu.h')
-rw-r--r--target-i386/cpu.h25
1 files changed, 22 insertions, 3 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 1d94a9dbd7..1fcbc82698 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -380,9 +380,14 @@
#define MSR_VM_HSAVE_PA 0xc0010117
-#define XSTATE_FP 1
-#define XSTATE_SSE 2
-#define XSTATE_YMM 4
+#define MSR_IA32_BNDCFGS 0x00000d90
+
+#define XSTATE_FP (1ULL << 0)
+#define XSTATE_SSE (1ULL << 1)
+#define XSTATE_YMM (1ULL << 2)
+#define XSTATE_BNDREGS (1ULL << 3)
+#define XSTATE_BNDCSR (1ULL << 4)
+
/* CPUID feature words */
typedef enum FeatureWord {
@@ -545,6 +550,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EBX_ERMS (1 << 9)
#define CPUID_7_0_EBX_INVPCID (1 << 10)
#define CPUID_7_0_EBX_RTM (1 << 11)
+#define CPUID_7_0_EBX_MPX (1 << 14)
#define CPUID_7_0_EBX_RDSEED (1 << 18)
#define CPUID_7_0_EBX_ADX (1 << 19)
#define CPUID_7_0_EBX_SMAP (1 << 20)
@@ -695,6 +701,16 @@ typedef union {
uint64_t q;
} MMXReg;
+typedef struct BNDReg {
+ uint64_t lb;
+ uint64_t ub;
+} BNDReg;
+
+typedef struct BNDCSReg {
+ uint64_t cfgu;
+ uint64_t sts;
+} BNDCSReg;
+
#ifdef HOST_WORDS_BIGENDIAN
#define XMM_B(n) _b[15 - (n)]
#define XMM_W(n) _w[7 - (n)]
@@ -908,6 +924,9 @@ typedef struct CPUX86State {
uint64_t xstate_bv;
XMMReg ymmh_regs[CPU_NB_REGS];
+ BNDReg bnd_regs[4];
+ BNDCSReg bndcs_regs;
+ uint64_t msr_bndcfgs;
uint64_t xcr0;