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| author | Avi Kivity <avi@redhat.com> | 2011-10-04 16:26:35 +0200 |
|---|---|---|
| committer | Marcelo Tosatti <mtosatti@redhat.com> | 2011-10-24 21:33:32 -0200 |
| commit | 21e87c4625f290824f4f05d098e576cda40421ce (patch) | |
| tree | 0a224637f8ff1537dfb2886ba37cece3a1656129 /target-i386/cpu.h | |
| parent | aa82ba549a3a88f7215e65956f3cb4bfd34835cc (diff) | |
| download | qemu-21e87c4625f290824f4f05d098e576cda40421ce.tar.gz | |
i386: wire up MSR_IA32_MISC_ENABLE
It's needed for its default value - bit 0 specifies that "rep movs" is
good enough for memcpy, and Linux may use a slower memcpu if it is not set,
depending on cpu family/model.
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Diffstat (limited to 'target-i386/cpu.h')
| -rw-r--r-- | target-i386/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 29412dc523..a08ce9d873 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -300,6 +300,10 @@ #define MSR_IA32_PERF_STATUS 0x198 +#define MSR_IA32_MISC_ENABLE 0x1a0 +/* Indicates good rep/movs microcode on some processors: */ +#define MSR_IA32_MISC_ENABLE_DEFAULT 1 + #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) @@ -691,6 +695,7 @@ typedef struct CPUX86State { uint64_t tsc_deadline; uint64_t mcg_status; + uint64_t msr_ia32_misc_enable; /* exception/interrupt handling */ int error_code; |