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| author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-02-03 02:42:36 +0000 |
|---|---|---|
| committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-02-03 02:42:36 +0000 |
| commit | 3d575329a53ad3b72b07cea0d8f97ccc000df6ff (patch) | |
| tree | cd85aad455cc76aa75311c9e5dc867da46b3727f /target-i386/cpu.h | |
| parent | 7c23b8920329180f48b8a147b629d8837709d201 (diff) | |
| download | qemu-3d575329a53ad3b72b07cea0d8f97ccc000df6ff.tar.gz | |
Make SVM env->cr[8] a valid register (patch from TeLeMan).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3950 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386/cpu.h')
| -rw-r--r-- | target-i386/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 2114cba920..819db7037b 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -493,7 +493,7 @@ typedef struct CPUX86State { SegmentCache gdt; /* only base and limit are used */ SegmentCache idt; /* only base and limit are used */ - target_ulong cr[5]; /* NOTE: cr1 is unused */ + target_ulong cr[9]; /* NOTE: cr1, cr5-7 are unused */ uint32_t a20_mask; /* FPU state */ |