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authorRichard Henderson <rth@twiddle.net>2015-11-18 12:55:47 +0100
committerRichard Henderson <rth@twiddle.net>2016-02-15 14:50:00 +1100
commit07929f2ab2ab9c9e01d4ae79f48f2b2476b715c8 (patch)
tree5df97c0cda565f1a3156b6dd6c60a8ea0902cf30 /target-i386/int_helper.c
parenta114d25d5b42600871d75929604c0b9fcc448ec0 (diff)
downloadqemu-07929f2ab2ab9c9e01d4ae79f48f2b2476b715c8.tar.gz
target-i386: Implement FSGSBASE
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-i386/int_helper.c')
-rw-r--r--target-i386/int_helper.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/target-i386/int_helper.c b/target-i386/int_helper.c
index 9d0d21e786..cf5bbb0481 100644
--- a/target-i386/int_helper.c
+++ b/target-i386/int_helper.c
@@ -470,3 +470,13 @@ target_ulong helper_pext(target_ulong src, target_ulong mask)
#include "shift_helper_template.h"
#undef SHIFT
#endif
+
+/* Test that BIT is enabled in CR4. If not, raise an illegal opcode
+ exception. This reduces the requirements for rare CR4 bits being
+ mapped into HFLAGS. */
+void helper_cr4_testbit(CPUX86State *env, uint32_t bit)
+{
+ if (unlikely((env->cr[4] & bit) == 0)) {
+ raise_exception_ra(env, EXCP06_ILLOP, GETPC());
+ }
+}