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| author | Richard Henderson <rth@twiddle.net> | 2015-07-02 15:57:14 +0100 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2016-02-13 07:59:59 +1100 |
| commit | f4f1110e4b34797ddfa87bb28f9518b9256778be (patch) | |
| tree | f88a66e3425e0e9d616200c2e566bd07a65dc44d /target-i386/misc_helper.c | |
| parent | c9cfe8f9fb21f086e24b3a8f7ccd9c06e4d8d9d6 (diff) | |
| download | qemu-f4f1110e4b34797ddfa87bb28f9518b9256778be.tar.gz | |
target-i386: Enable control registers for MPX
Enable and disable at CPL changes, MSR changes, and XRSTOR changes.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-i386/misc_helper.c')
| -rw-r--r-- | target-i386/misc_helper.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c index 460257f6bc..5fbab8fd0c 100644 --- a/target-i386/misc_helper.c +++ b/target-i386/misc_helper.c @@ -361,6 +361,12 @@ void helper_wrmsr(CPUX86State *env) case MSR_IA32_MISC_ENABLE: env->msr_ia32_misc_enable = val; break; + case MSR_IA32_BNDCFGS: + /* FIXME: #GP if reserved bits are set. */ + /* FIXME: Extend highest implemented bit of linear address. */ + env->msr_bndcfgs = val; + cpu_sync_bndcs_hflags(env); + break; default: if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + @@ -506,6 +512,9 @@ void helper_rdmsr(CPUX86State *env) case MSR_IA32_MISC_ENABLE: val = env->msr_ia32_misc_enable; break; + case MSR_IA32_BNDCFGS: + val = env->msr_bndcfgs; + break; default: if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + |