diff options
| author | Huang Ying <ying.huang@intel.com> | 2009-06-23 10:05:14 +0800 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2009-07-09 16:04:53 -0500 |
| commit | 79c4f6b08009a1d23177c2be8bd003253cf3686a (patch) | |
| tree | c9a9e72451d20ba2ae8e0f5a14301522281add70 /target-i386/op_helper.c | |
| parent | 2152390dca9975b1aaaa6f0518ebdd359477905b (diff) | |
| download | qemu-79c4f6b08009a1d23177c2be8bd003253cf3686a.tar.gz | |
QEMU: MCE: Add MCE simulation to qemu/tcg
- MCE features are initialized when VCPU is intialized according to CPUID.
- A monitor command "mce" is added to inject a MCE.
- A new interrupt mask: CPU_INTERRUPT_MCE is added to inject the MCE.
aliguori: fix build for linux-user
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'target-i386/op_helper.c')
| -rw-r--r-- | target-i386/op_helper.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c index bd1769c528..ed22c7a650 100644 --- a/target-i386/op_helper.c +++ b/target-i386/op_helper.c @@ -3133,7 +3133,23 @@ void helper_wrmsr(void) case MSR_MTRRdefType: env->mtrr_deftype = val; break; + case MSR_MCG_STATUS: + env->mcg_status = val; + break; + case MSR_MCG_CTL: + if ((env->mcg_cap & MCG_CTL_P) + && (val == 0 || val == ~(uint64_t)0)) + env->mcg_ctl = val; + break; default: + if ((uint32_t)ECX >= MSR_MC0_CTL + && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) { + uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL; + if ((offset & 0x3) != 0 + || (val == 0 || val == ~(uint64_t)0)) + env->mce_banks[offset] = val; + break; + } /* XXX: exception ? */ break; } @@ -3252,7 +3268,25 @@ void helper_rdmsr(void) /* XXX: exception ? */ val = 0; break; + case MSR_MCG_CAP: + val = env->mcg_cap; + break; + case MSR_MCG_CTL: + if (env->mcg_cap & MCG_CTL_P) + val = env->mcg_ctl; + else + val = 0; + break; + case MSR_MCG_STATUS: + val = env->mcg_status; + break; default: + if ((uint32_t)ECX >= MSR_MC0_CTL + && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) { + uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL; + val = env->mce_banks[offset]; + break; + } /* XXX: exception ? */ val = 0; break; |