diff options
| author | Andre Przywara <andre.przywara@amd.com> | 2009-10-23 13:44:31 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2009-10-23 17:10:36 +0200 |
| commit | 31501a714b7a99fd7b937a45558ed02aa1b57d58 (patch) | |
| tree | ff6ad928f74dd654a02770cd90a799ae8d17a83e /target-i386/op_helper.c | |
| parent | cb2dbfc3516f3fc6b49c52c759b2023d5a824b52 (diff) | |
| download | qemu-31501a714b7a99fd7b937a45558ed02aa1b57d58.tar.gz | |
target-i386: implement lzcnt emulation
lzcnt is a AMD Phenom/Barcelona added instruction returning the
number of leading zero bits in a word.
As this is similar to the "bsr" instruction, reuse the existing
code. There need to be some more changes, though, as lzcnt always
returns a valid value (in opposite to bsr, which has a special
case when the operand is 0).
lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5).
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-i386/op_helper.c')
| -rw-r--r-- | target-i386/op_helper.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c index 26fe612048..5eea3221b3 100644 --- a/target-i386/op_helper.c +++ b/target-i386/op_helper.c @@ -5479,11 +5479,14 @@ target_ulong helper_bsf(target_ulong t0) return count; } -target_ulong helper_bsr(target_ulong t0) +target_ulong helper_lzcnt(target_ulong t0, int wordsize) { int count; target_ulong res, mask; - + + if (wordsize > 0 && t0 == 0) { + return wordsize; + } res = t0; count = TARGET_LONG_BITS - 1; mask = (target_ulong)1 << (TARGET_LONG_BITS - 1); @@ -5491,9 +5494,16 @@ target_ulong helper_bsr(target_ulong t0) count--; res <<= 1; } + if (wordsize > 0) { + return wordsize - 1 - count; + } return count; } +target_ulong helper_bsr(target_ulong t0) +{ + return helper_lzcnt(t0, 0); +} static int compute_all_eflags(void) { |