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| author | Richard Henderson <rth@twiddle.net> | 2013-01-23 16:44:37 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-02-18 15:52:05 -0800 |
| commit | bc4b43dc2fe88712ad921c05fc1ab9ebc4cb6778 (patch) | |
| tree | 125552316f32948a4db967277e9e6520e9f35c3a /target-i386/translate.c | |
| parent | c7ab7565bc6d52cc140230aa4d0533d13d89c8b1 (diff) | |
| download | qemu-bc4b43dc2fe88712ad921c05fc1ab9ebc4cb6778.tar.gz | |
target-i386: Implement BLSR, BLSMSK, BLSI
Do all of group 17 at one time for ease.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-i386/translate.c')
| -rw-r--r-- | target-i386/translate.c | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c index d742fe3693..2322d5c838 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -209,6 +209,7 @@ static const uint8_t cc_op_live[CC_OP_NB] = { [CC_OP_DECB ... CC_OP_DECQ] = USES_CC_DST | USES_CC_SRC, [CC_OP_SHLB ... CC_OP_SHLQ] = USES_CC_DST | USES_CC_SRC, [CC_OP_SARB ... CC_OP_SARQ] = USES_CC_DST | USES_CC_SRC, + [CC_OP_BMILGB ... CC_OP_BMILGQ] = USES_CC_DST | USES_CC_SRC, }; static void set_cc_op(DisasContext *s, CCOp op) @@ -988,6 +989,11 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, .mask = -1 }; + case CC_OP_BMILGB ... CC_OP_BMILGQ: + size = s->cc_op - CC_OP_BMILGB; + t0 = gen_ext_tl(reg, cpu_cc_src, size, false); + return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 }; + case CC_OP_EFLAGS: case CC_OP_SARB ... CC_OP_SARQ: /* CC_SRC & 1 */ @@ -4066,6 +4072,48 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } break; + case 0x0f3: + case 0x1f3: + case 0x2f3: + case 0x3f3: /* Group 17 */ + if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1) + || !(s->prefix & PREFIX_VEX) + || s->vex_l != 0) { + goto illegal_op; + } + ot = s->dflag == 2 ? OT_QUAD : OT_LONG; + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); + + switch (reg & 7) { + case 1: /* blsr By,Ey */ + tcg_gen_neg_tl(cpu_T[1], cpu_T[0]); + tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); + gen_op_mov_reg_T0(ot, s->vex_v); + gen_op_update2_cc(); + set_cc_op(s, CC_OP_BMILGB + ot); + break; + + case 2: /* blsmsk By,Ey */ + tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); + tcg_gen_subi_tl(cpu_T[0], cpu_T[0], 1); + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_cc_src); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + set_cc_op(s, CC_OP_BMILGB + ot); + break; + + case 3: /* blsi By, Ey */ + tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); + tcg_gen_subi_tl(cpu_T[0], cpu_T[0], 1); + tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_cc_src); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + set_cc_op(s, CC_OP_BMILGB + ot); + break; + + default: + goto illegal_op; + } + break; + default: goto illegal_op; } |