diff options
| author | Richard Henderson <rth@twiddle.net> | 2013-01-23 13:53:51 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-02-18 15:03:57 -0800 |
| commit | be10b289d697420b6e0d8d1a681aa64555066639 (patch) | |
| tree | e64efd26529cdfbb976f6c59e1ff05bb99b74b8e /target-i386/translate.c | |
| parent | 2cb4764577f270eec259123955a6396ad6a2f161 (diff) | |
| download | qemu-be10b289d697420b6e0d8d1a681aa64555066639.tar.gz | |
target-i386: optimize setle
And allow gen_setcc_slow to operate on cpu_cc_src.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-i386/translate.c')
| -rw-r--r-- | target-i386/translate.c | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c index dab69839a7..fea43c702e 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -1045,7 +1045,6 @@ static void gen_compute_eflags_z(DisasContext *s, TCGv reg, bool inv) static void gen_setcc_slow(DisasContext *s, int jcc_op, TCGv reg, bool inv) { - assert(!TCGV_EQUAL(reg, cpu_cc_src)); switch(jcc_op) { case JCC_O: gen_compute_eflags_o(s, reg); @@ -1072,20 +1071,18 @@ static void gen_setcc_slow(DisasContext *s, int jcc_op, TCGv reg, bool inv) break; case JCC_L: gen_compute_eflags(s); - tcg_gen_shri_tl(reg, cpu_cc_src, 11); /* CC_O */ - tcg_gen_shri_tl(cpu_tmp0, cpu_cc_src, 7); /* CC_S */ + tcg_gen_shri_tl(cpu_tmp0, cpu_cc_src, 11); /* CC_O */ + tcg_gen_shri_tl(reg, cpu_cc_src, 7); /* CC_S */ tcg_gen_xor_tl(reg, reg, cpu_tmp0); tcg_gen_andi_tl(reg, reg, 1); break; default: case JCC_LE: gen_compute_eflags(s); - tcg_gen_shri_tl(reg, cpu_cc_src, 11); /* CC_O */ - tcg_gen_shri_tl(cpu_tmp4, cpu_cc_src, 7); /* CC_S */ - tcg_gen_shri_tl(cpu_tmp0, cpu_cc_src, 6); /* CC_Z */ - tcg_gen_xor_tl(reg, reg, cpu_tmp4); - tcg_gen_or_tl(reg, reg, cpu_tmp0); - tcg_gen_andi_tl(reg, reg, 1); + tcg_gen_shri_tl(cpu_tmp0, cpu_cc_src, 4); /* CC_O -> CC_S */ + tcg_gen_xor_tl(reg, cpu_tmp0, cpu_cc_src); + tcg_gen_andi_tl(reg, reg, CC_S | CC_Z); + tcg_gen_setcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, reg, reg, 0); break; } if (inv) { |