diff options
| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2004-02-03 23:27:13 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2004-02-03 23:27:13 +0000 |
| commit | 64a595f26ae04ee386a3ce725c9222535dc28022 (patch) | |
| tree | 6297d5f2fe5d74037f2323f7b5c1cced6b39fa03 /target-i386 | |
| parent | 3ad9a57e4f0471d73e88a73f17a0e975a162c4e7 (diff) | |
| download | qemu-64a595f26ae04ee386a3ce725c9222535dc28022.tar.gz | |
cleanup
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@595 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386')
| -rw-r--r-- | target-i386/cpu.h | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index a93486cbe4..676e6ceae3 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -133,6 +133,8 @@ #define CR4_TSD_MASK (1 << 2) #define CR4_DE_MASK (1 << 3) #define CR4_PSE_MASK (1 << 4) +#define CR4_PAE_MASK (1 << 5) +#define CR4_PGE_MASK (1 << 7) #define PG_PRESENT_BIT 0 #define PG_RW_BIT 1 @@ -309,6 +311,7 @@ typedef struct CPUX86State { int user_mode_only; /* user mode only simulation */ /* soft mmu support */ + uint32_t a20_mask; /* 0 = kernel, 1 = user */ CPUTLBEntry tlb_read[2][CPU_TLB_SIZE]; CPUTLBEntry tlb_write[2][CPU_TLB_SIZE]; @@ -396,13 +399,11 @@ void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32); struct siginfo; int cpu_x86_signal_handler(int host_signum, struct siginfo *info, void *puc); - -/* MMU defines */ -void cpu_x86_init_mmu(CPUX86State *env); -extern int a20_enabled; - void cpu_x86_set_a20(CPUX86State *env, int a20_state); +/* will be suppressed */ +void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); + /* used to debug */ #define X86_DUMP_FPU 0x0001 /* dump FPU state too */ #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ |