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| author | Michal Simek <monstr@monstr.eu> | 2011-03-04 14:39:31 +0100 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@petalogix.com> | 2011-03-11 15:24:37 +0100 |
| commit | c4374bb7533c2c8f999526148113012dc1f436ae (patch) | |
| tree | c6601dd874f00447762a045d8c7dfcd252cf41a0 /target-microblaze/cpu.h | |
| parent | 73ad9e62a3d78c909505c04113aed3dac60f5b2d (diff) | |
| download | qemu-c4374bb7533c2c8f999526148113012dc1f436ae.tar.gz | |
microblaze: Add PVR for writeback cache, endians
Specify PVR for writeback cache, endians and others.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
Diffstat (limited to 'target-microblaze/cpu.h')
| -rw-r--r-- | target-microblaze/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 3aa28bfd40..14d4d42730 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -110,6 +110,9 @@ struct CPUMBState; #define PVR0_USE_ICACHE_MASK 0x02000000 #define PVR0_USE_DCACHE_MASK 0x01000000 #define PVR0_USE_MMU 0x00800000 /* new */ +#define PVR0_USE_BTC 0x00400000 +#define PVR0_ENDI 0x00200000 +#define PVR0_FAULT 0x00100000 #define PVR0_VERSION_MASK 0x0000FF00 #define PVR0_USER1_MASK 0x000000FF @@ -169,6 +172,7 @@ struct CPUMBState; #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 +#define PVR5_DCACHE_WRITEBACK_MASK 0x00004000 /* ICache base address PVR mask */ #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF |