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| author | Paul Brook <paul@codesourcery.com> | 2009-07-09 17:45:17 +0100 |
|---|---|---|
| committer | Paul Brook <paul@codesourcery.com> | 2009-07-09 17:45:17 +0100 |
| commit | 590bc601d800d16a77676926898019f7285bd615 (patch) | |
| tree | 85cfd216edb9e8a3068cb4848f238e1fe4fdef58 /target-mips/cpu.h | |
| parent | ff867ddcbd55af7becd2328a454e0158018fb50e (diff) | |
| download | qemu-590bc601d800d16a77676926898019f7285bd615.tar.gz | |
MIPS atomic instructions
Implement MIPS ll/sc instructions using atomic compare+exchange.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 6ebb82bccb..bb9a49b985 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -375,6 +375,9 @@ struct CPUMIPSState { int32_t CP0_Config7; /* XXX: Maybe make LLAddr per-TC? */ target_ulong CP0_LLAddr; + target_ulong llval; + target_ulong llnewval; + target_ulong llreg; target_ulong CP0_WatchLo[8]; int32_t CP0_WatchHi[8]; target_ulong CP0_XContext; @@ -559,6 +562,8 @@ enum { EXCP_LAST = EXCP_CACHE, }; +/* Dummy exception for conditional stores. */ +#define EXCP_SC 0x100 int cpu_mips_exec(CPUMIPSState *s); CPUMIPSState *cpu_mips_init(const char *cpu_model); |