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| author | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-01-17 19:25:57 +0100 |
|---|---|---|
| committer | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-02-10 16:46:28 +0100 |
| commit | b4dd99a3636f5a3044dfd9dba7653ca377a9aeba (patch) | |
| tree | 0ec10e09bdec7994ad111ba47732b7820691c128 /target-mips/cpu.h | |
| parent | b4160af160ba045e3a25013b4def4a39f09cbb78 (diff) | |
| download | qemu-b4dd99a3636f5a3044dfd9dba7653ca377a9aeba.tar.gz | |
target-mips: add support for CP0_Config5
Add CP0_Config5, define rw_bitmask and enable modifications.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index e8216abe09..60c80617a5 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -73,6 +73,7 @@ struct CPUMIPSFPUContext { float_status fp_status; /* fpu implementation/revision register (fir) */ uint32_t fcr0; +#define FCR0_UFRP 28 #define FCR0_F64 22 #define FCR0_L 21 #define FCR0_W 20 @@ -371,6 +372,15 @@ struct CPUMIPSState { uint32_t CP0_Config4; uint32_t CP0_Config4_rw_bitmask; #define CP0C4_M 31 + uint32_t CP0_Config5; + uint32_t CP0_Config5_rw_bitmask; +#define CP0C5_M 31 +#define CP0C5_K 30 +#define CP0C5_CV 29 +#define CP0C5_EVA 28 +#define CP0C5_MSAEn 27 +#define CP0C5_UFR 2 +#define CP0C5_NFExists 0 int32_t CP0_Config6; int32_t CP0_Config7; /* XXX: Maybe make LLAddr per-TC? */ |