diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-18 11:57:27 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-18 11:57:27 +0000 |
| commit | f01be154589f6e137195d9cc28d1296d885e4eea (patch) | |
| tree | b8effdfbfaddddcbbd81e876a62ff18da6686c0f /target-mips/cpu.h | |
| parent | a1cf28f469883f89e83d6026986254806e88c235 (diff) | |
| download | qemu-f01be154589f6e137195d9cc28d1296d885e4eea.tar.gz | |
Move the active FPU registers into env again, and use more TCG registers
to access them.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5252 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 8918a868e2..9173452451 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -84,9 +84,9 @@ struct CPUMIPSFPUContext { #define FCR0_REV 0 /* fcsr */ uint32_t fcr31; -#define SET_FP_COND(num,env) do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) -#define CLEAR_FP_COND(num,env) do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) -#define GET_FP_COND(env) ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1)) +#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) +#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) +#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) @@ -132,6 +132,7 @@ typedef struct mips_def_t mips_def_t; #define MIPS_SHADOW_SET_MAX 16 #define MIPS_TC_MAX 5 +#define MIPS_FPU_MAX 1 #define MIPS_DSP_ACC 4 typedef struct TCState TCState; @@ -170,11 +171,12 @@ struct TCState { typedef struct CPUMIPSState CPUMIPSState; struct CPUMIPSState { TCState active_tc; + CPUMIPSFPUContext active_fpu; CPUMIPSMVPContext *mvp; CPUMIPSTLBContext *tlb; - CPUMIPSFPUContext *fpu; uint32_t current_tc; + uint32_t current_fpu; uint32_t SEGBITS; uint32_t PABITS; @@ -404,6 +406,7 @@ struct CPUMIPSState { int32_t CP0_DESAVE; /* We waste some space so we can handle shadow registers like TCs. */ TCState tcs[MIPS_SHADOW_SET_MAX]; + CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; /* Qemu */ int error_code; uint32_t hflags; /* CPU State */ |