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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-17 15:26:47 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-17 15:26:47 +0000 |
| commit | fcb4a419f52e538b68510a68f30d8834dd211155 (patch) | |
| tree | dde98a86a29d51b875dba98d448e1ae18c0f691d /target-mips/cpu.h | |
| parent | 04f20795ac815cf3ad5d1fdc99462f60eb871f25 (diff) | |
| download | qemu-fcb4a419f52e538b68510a68f30d8834dd211155.tar.gz | |
Choose number of TLBs at runtime, by Herve Poussineau.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2693 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index c91e2cac49..36b890efb0 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -99,6 +99,7 @@ struct CPUMIPSState { #if defined(MIPS_USES_R4K_TLB) tlb_t tlb[MIPS_TLB_MAX]; uint32_t tlb_in_use; + uint32_t nb_tlb; #endif int32_t CP0_Index; int32_t CP0_Random; |