diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-23 16:14:22 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-23 16:14:22 +0000 |
| commit | 0eaef5aa01a8e27b57a46217a0b65cc1d30a5d41 (patch) | |
| tree | 54075667b5317724514dc1aed55a6d578e05b072 /target-mips/cpu.h | |
| parent | 477e3edf8be5f0b998d19766198b6cf6b847557f (diff) | |
| download | qemu-0eaef5aa01a8e27b57a46217a0b65cc1d30a5d41.tar.gz | |
Less hardcoding of TARGET_USER_ONLY.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4928 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 3ec867a722..8918a868e2 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -445,17 +445,12 @@ struct CPUMIPSState { uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ int insn_flags; /* Supported instruction set */ -#ifdef CONFIG_USER_ONLY - target_ulong tls_value; -#endif + target_ulong tls_value; /* For usermode emulation */ CPU_COMMON const mips_def_t *cpu_model; -#ifndef CONFIG_USER_ONLY void *irq[8]; -#endif - struct QEMUTimer *timer; /* Internal timer */ }; @@ -494,7 +489,6 @@ static inline int cpu_mmu_index (CPUState *env) return env->hflags & MIPS_HFLAG_KSU; } -#if defined(CONFIG_USER_ONLY) static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) { if (newsp) @@ -502,7 +496,6 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) env->active_tc.gpr[7] = 0; env->active_tc.gpr[2] = 0; } -#endif #include "cpu-all.h" |