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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-01-24 01:47:51 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-01-24 01:47:51 +0000 |
| commit | 4de9b249d37c1b382cc3e5a21fad1b4a11cec2fa (patch) | |
| tree | 3991d58b09108b5c18a4388b2c2a8b6cb8f57142 /target-mips/cpu.h | |
| parent | 30c4bbace19e802979009cc5c16fb4e14dc6bda6 (diff) | |
| download | qemu-4de9b249d37c1b382cc3e5a21fad1b4a11cec2fa.tar.gz | |
Reworking MIPS interrupt handling, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2350 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 8781e3098d..3c99054d6d 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -158,6 +158,7 @@ struct CPUMIPSState { #define CP0Ca_IV 23 #define CP0Ca_WP 22 #define CP0Ca_IP 8 +#define CP0Ca_IP_mask 0x0000FF00 #define CP0Ca_EC 2 target_ulong CP0_EPC; int32_t CP0_PRid; |