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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-03-23 00:43:28 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-03-23 00:43:28 +0000 |
| commit | e397ee3382a34c65b0fb93514c3eef5c31715d3c (patch) | |
| tree | cd0afd9013624ab292d6a54998e4b1e2cf727390 /target-mips/cpu.h | |
| parent | 51789c410beb34423b1188a6b6e069fe8b68aebe (diff) | |
| download | qemu-e397ee3382a34c65b0fb93514c3eef5c31715d3c.tar.gz | |
Fix enough FPU/R2 support to get 24Kf going.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2528 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 276910aaed..f0f3ab2d73 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -203,6 +203,8 @@ struct CPUMIPSState { #define CP0C3_MT 2 #define CP0C3_SM 1 #define CP0C3_TL 0 + int32_t CP0_Config6; + int32_t CP0_Config7; target_ulong CP0_LLAddr; target_ulong CP0_WatchLo; int32_t CP0_WatchHi; |