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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-23 08:24:25 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-23 08:24:25 +0000 |
| commit | fd88b6abab9a4425505b292b5fedbad31d0dfe4f (patch) | |
| tree | 33723cfca31d3cf54b6c9d103c002e34ab97c374 /target-mips/cpu.h | |
| parent | df1561e22df42643d769aacdcc7d6d239f243366 (diff) | |
| download | qemu-fd88b6abab9a4425505b292b5fedbad31d0dfe4f.tar.gz | |
The 24k wants more watch and srsmap registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2849 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index e0f03eda73..9cddc174d2 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -216,8 +216,8 @@ struct CPUMIPSState { int32_t CP0_Config6; int32_t CP0_Config7; target_ulong CP0_LLAddr; - target_ulong CP0_WatchLo; - int32_t CP0_WatchHi; + target_ulong CP0_WatchLo[8]; + int32_t CP0_WatchHi[8]; target_ulong CP0_XContext; int32_t CP0_Framemask; int32_t CP0_Debug; |