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| author | Nathan Froyd <froydnj@codesourcery.com> | 2010-06-08 13:30:01 -0700 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-06-09 16:10:51 +0200 |
| commit | bbfa8f72e99baa0514b2b39e671830cf9a3adc44 (patch) | |
| tree | 29d718f8b97573eb4b4b359e352159d696c0a19f /target-mips/cpu.h | |
| parent | 3c824109da076d2a1df4b798f9df81b385131f92 (diff) | |
| download | qemu-bbfa8f72e99baa0514b2b39e671830cf9a3adc44.tar.gz | |
target-mips: add microMIPS exception handler support
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exception
handlers. The ISA mode is selectable via a user-writable CP0.Config3
flag.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 7285636b68..c21b8e43ff 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -363,6 +363,7 @@ struct CPUMIPSState { #define CP0C2_SA 0 int32_t CP0_Config3; #define CP0C3_M 31 +#define CP0C3_ISA_ON_EXC 16 #define CP0C3_DSPP 10 #define CP0C3_LPA 7 #define CP0C3_VEIC 6 |