diff options
| author | Maciej W. Rozycki <macro@codesourcery.com> | 2014-11-10 13:46:35 +0000 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-12-16 12:45:19 +0000 |
| commit | 81a423e6c6d3ccaa79de4e58024369c660c1eeb4 (patch) | |
| tree | ccc5e90b146ffa3e0d8a6c40888b063cae188961 /target-mips/gdbstub.c | |
| parent | f88f79ec9df06d26d84e1d2e0c02d2634b4d8583 (diff) | |
| download | qemu-81a423e6c6d3ccaa79de4e58024369c660c1eeb4.tar.gz | |
target-mips: Correct the writes to Status and Cause registers via gdbstub
Make writes to CP0.Status and CP0.Cause have the same effect as
executing corresponding MTC0 instructions would in Kernel Mode. Also
ignore writes in the user emulation mode.
Currently for requests from the GDB stub we write all the bits across
both registers, ignoring any read-only locations, and do not synchronise
the environment to evaluate side effects. We also write these registers
in the user emulation mode even though a real kernel presents them as
read only.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/gdbstub.c')
| -rw-r--r-- | target-mips/gdbstub.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c index e86df0e57c..964e6a7733 100644 --- a/target-mips/gdbstub.c +++ b/target-mips/gdbstub.c @@ -112,7 +112,9 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } switch (n) { case 32: - env->CP0_Status = tmp; +#ifndef CONFIG_USER_ONLY + cpu_mips_store_status(env, tmp); +#endif break; case 33: env->active_tc.LO[0] = tmp; @@ -124,7 +126,9 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->CP0_BadVAddr = tmp; break; case 36: - env->CP0_Cause = tmp; +#ifndef CONFIG_USER_ONLY + cpu_mips_store_cause(env, tmp); +#endif break; case 37: env->active_tc.PC = tmp & ~(target_ulong)1; |