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authorLeon Alrae <leon.alrae@imgtec.com>2015-11-19 19:15:35 +0000
committerLeon Alrae <leon.alrae@imgtec.com>2015-11-24 11:01:03 +0000
commitf93c3a8d0c0c1038dbe1e957eb8ab92671137975 (patch)
tree00969bbc0675fd9851c1678f8c829846221e192c /target-mips/kvm_mips.h
parent7871abb94c2f4adc39f2487f6edf5e69ba872a65 (diff)
downloadqemu-f93c3a8d0c0c1038dbe1e957eb8ab92671137975.tar.gz
target-mips: flush QEMU TLB when disabling 64-bit addressing
CP0.Status.KX/SX/UX bits are responsible for enabling access to 64-bit Kernel/Supervisor/User Segments. If bit is cleared an access to corresponding segment should generate Address Error Exception. However, the guest may still be able to access some pages belonging to the disabled 64-bit segment because we forget to flush QEMU TLB. This patch fixes it. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/kvm_mips.h')
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