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| author | Maciej W. Rozycki <macro@codesourcery.com> | 2014-11-03 18:47:45 +0000 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-12-16 12:45:19 +0000 |
| commit | 800675f11742b6080e40d17b8d5f35d3a5fc5724 (patch) | |
| tree | 4c045b49cd4895afa41cecfc2ff3304fc1096f1e /target-mips/machine.c | |
| parent | dfa9c2a0f4d0a0c8b2c1449ecdbb1297427e1560 (diff) | |
| download | qemu-800675f11742b6080e40d17b8d5f35d3a5fc5724.tar.gz | |
target-mips: Correct the handling of register #72 on writes
Fix an off-by-one error in `mips_cpu_gdb_write_register' for register
matching how `mips_cpu_gdb_read_register' handles it. This register
slot is a fake anyway, there's nothing in hardware that corresponds to
it.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/machine.c')
0 files changed, 0 insertions, 0 deletions