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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-02-28 22:37:42 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-02-28 22:37:42 +0000 |
| commit | 36d239587370c6ccfc53d7f6acc624ce5d61fe84 (patch) | |
| tree | 43d11aaf52a198b5544bbb7e878c6cb633dec299 /target-mips/mips-defs.h | |
| parent | 54d43f70e3b003b5f24ef30ea361e034c2813d9f (diff) | |
| download | qemu-36d239587370c6ccfc53d7f6acc624ce5d61fe84.tar.gz | |
MIPS FPU dynamic activation, part 1, by Herve Poussineau.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2463 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/mips-defs.h')
| -rw-r--r-- | target-mips/mips-defs.h | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index 83480c6ab4..a78bef55ec 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -45,19 +45,14 @@ 2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache, no coprocessor2 attached, no MDMX support attached, no performance counters, watch registers present, - no code compression, EJTAG present, FPU enable bit depending on - MIPS_USES_FPU */ -#define MIPS_CONFIG1_1 \ + no code compression, EJTAG present, no FPU */ +#define MIPS_CONFIG1 \ ((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) | \ (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \ (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \ (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ - (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP)) -#ifdef MIPS_USES_FPU -#define MIPS_CONFIG1 (MIPS_CONFIG1_1 | (1 << CP0C1_FP)) -#else -#define MIPS_CONFIG1 (MIPS_CONFIG1_1 | (0 << CP0C1_FP)) -#endif + (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ + (0 << CP0C1_FP)) /* Have config3, no tertiary/secondary caches implemented */ #define MIPS_CONFIG2 \ ((1 << CP0C2_M)) |