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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-12-02 07:14:17 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-12-02 07:14:17 +0000 |
| commit | dab6322b86bb9d9cf86847ceb055f1b99f1e772a (patch) | |
| tree | 2e61945b1dc140bfffdfbcf95bdcd5c620fa403a /target-mips/mips-defs.h | |
| parent | c3b5bc8ab325bd3aee46ea5c0884c9e6f1636ccb (diff) | |
| download | qemu-dab6322b86bb9d9cf86847ceb055f1b99f1e772a.tar.gz | |
Larger physical address space for 32-bit MIPS.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3765 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/mips-defs.h')
| -rw-r--r-- | target-mips/mips-defs.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index 251fa359dc..76ea8d019b 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -14,6 +14,9 @@ #define TARGET_LONG_BITS 32 #endif +/* Even MIPS32 can have 36 bits physical address space. */ +#define TARGET_PHYS_ADDR_BITS 64 + /* Masks used to mark instructions to indicate which ISA level they were introduced in. */ #define ISA_MIPS1 0x00000001 |