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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-09-24 12:48:00 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-09-24 12:48:00 +0000 |
| commit | e189e7486867e36c35f99cbac27d503ce4e7c71d (patch) | |
| tree | ac7f7d77ee235b50b3db039b78d6965f807daca7 /target-mips/mips-defs.h | |
| parent | 92a34c10b595ae01ff55c385b9867363ac91e0eb (diff) | |
| download | qemu-e189e7486867e36c35f99cbac27d503ce4e7c71d.tar.gz | |
Per-CPU instruction decoding implementation, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3228 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/mips-defs.h')
| -rw-r--r-- | target-mips/mips-defs.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index 6f012a964e..a796c7e096 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -14,6 +14,41 @@ #define TARGET_LONG_BITS 32 #endif +/* Masks used to mark instructions to indicate which ISA level they + were introduced in. */ +#define ISA_MIPS1 0x00000001 +#define ISA_MIPS2 0x00000002 +#define ISA_MIPS3 0x00000004 +#define ISA_MIPS4 0x00000008 +#define ISA_MIPS5 0x00000010 +#define ISA_MIPS32 0x00000020 +#define ISA_MIPS32R2 0x00000040 +#define ISA_MIPS64 0x00000080 +#define ISA_MIPS64R2 0x00000100 + +/* MIPS ASE */ +#define ASE_MIPS16 0x00001000 +#define ASE_MIPS3D 0x00002000 +#define ASE_MDMX 0x00004000 +#define ASE_DSP 0x00008000 +#define ASE_DSPR2 0x00010000 + +/* Chip specific instructions. */ +/* Currently void */ + +/* MIPS CPU defines. */ +#define CPU_MIPS1 (ISA_MIPS1) +#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) +#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) +#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) +#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) + +#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) +#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) + +#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) +#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) + /* Strictly follow the architecture standard: - Disallow "special" instruction handling for PMON/SPIM. Note that we still maintain Count/Compare to match the host clock. */ |