diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-12-25 20:46:56 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-12-25 20:46:56 +0000 |
| commit | e9c71dd1c1f5aeb3732261a02dcfae031973f053 (patch) | |
| tree | de9b88fe2a6e0ffbb6b2f1fa63f401e14aa66e6a /target-mips/mips-defs.h | |
| parent | 29fe0e3490ef63f564f426fc526d4415f44e7052 (diff) | |
| download | qemu-e9c71dd1c1f5aeb3732261a02dcfae031973f053.tar.gz | |
Support for VR5432, and some of its special instructions. Original patch
by Dirk Behme.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3859 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/mips-defs.h')
| -rw-r--r-- | target-mips/mips-defs.h | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index 76ea8d019b..2d0c1383dd 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -4,7 +4,7 @@ /* If we want to use host float regs... */ //#define USE_HOST_FLOAT_REGS -/* real pages are variable size... */ +/* Real pages are variable size... */ #define TARGET_PAGE_BITS 12 #define MIPS_TLB_MAX 128 @@ -29,7 +29,7 @@ #define ISA_MIPS64 0x00000080 #define ISA_MIPS64R2 0x00000100 -/* MIPS ASE */ +/* MIPS ASEs. */ #define ASE_MIPS16 0x00001000 #define ASE_MIPS3D 0x00002000 #define ASE_MDMX 0x00004000 @@ -38,19 +38,23 @@ #define ASE_MT 0x00020000 #define ASE_SMARTMIPS 0x00040000 -/* Chip specific instructions. */ -/* Currently void */ +/* Chip specific instructions. */ +#define INSN_VR54XX 0x80000000 -/* MIPS CPU defines. */ +/* MIPS CPU defines. */ #define CPU_MIPS1 (ISA_MIPS1) #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) +#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) + #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) +/* MIPS Technologies "Release 1" */ #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) +/* MIPS Technologies "Release 2" */ #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) |