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| author | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-01-17 19:25:57 +0100 |
|---|---|---|
| committer | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-02-10 16:46:28 +0100 |
| commit | b4dd99a3636f5a3044dfd9dba7653ca377a9aeba (patch) | |
| tree | 0ec10e09bdec7994ad111ba47732b7820691c128 /target-mips/translate.c | |
| parent | b4160af160ba045e3a25013b4def4a39f09cbb78 (diff) | |
| download | qemu-b4dd99a3636f5a3044dfd9dba7653ca377a9aeba.tar.gz | |
target-mips: add support for CP0_Config5
Add CP0_Config5, define rw_bitmask and enable modifications.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index db2f430bc6..02a90cb532 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -4409,7 +4409,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4)); rn = "Config4"; break; - /* 5 is reserved */ + case 5: + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); + rn = "Config5"; + break; /* 6,7 are implementation dependent */ case 6: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); @@ -4991,7 +4994,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) rn = "Config4"; ctx->bstate = BS_STOP; break; - /* 5 is reserved */ + case 5: + gen_helper_mtc0_config5(cpu_env, arg); + rn = "Config5"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; /* 6,7 are implementation dependent */ case 6: /* ignored */ @@ -15927,6 +15935,8 @@ void cpu_state_reset(CPUMIPSState *env) env->CP0_Config3 = env->cpu_model->CP0_Config3; env->CP0_Config4 = env->cpu_model->CP0_Config4; env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask; + env->CP0_Config5 = env->cpu_model->CP0_Config5; + env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask; env->CP0_Config6 = env->cpu_model->CP0_Config6; env->CP0_Config7 = env->cpu_model->CP0_Config7; env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask |