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| author | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-01-17 19:25:57 +0100 |
|---|---|---|
| committer | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-02-10 16:46:28 +0100 |
| commit | b4dd99a3636f5a3044dfd9dba7653ca377a9aeba (patch) | |
| tree | 0ec10e09bdec7994ad111ba47732b7820691c128 /target-mips/translate_init.c | |
| parent | b4160af160ba045e3a25013b4def4a39f09cbb78 (diff) | |
| download | qemu-b4dd99a3636f5a3044dfd9dba7653ca377a9aeba.tar.gz | |
target-mips: add support for CP0_Config5
Add CP0_Config5, define rw_bitmask and enable modifications.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index a0398cdc9a..3d4dc88002 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -48,6 +48,9 @@ #define MIPS_CONFIG4 \ ((0 << CP0C4_M)) +#define MIPS_CONFIG5 \ +((0 << CP0C5_M)) + /* MMU types, the first four entries have the same layout as the CP0C0_MT field. */ enum mips_mmu_types { @@ -69,6 +72,8 @@ struct mips_def_t { int32_t CP0_Config3; int32_t CP0_Config4; int32_t CP0_Config4_rw_bitmask; + int32_t CP0_Config5; + int32_t CP0_Config5_rw_bitmask; int32_t CP0_Config6; int32_t CP0_Config7; target_ulong CP0_LLAddr_rw_bitmask; @@ -351,8 +356,13 @@ static const mips_def_t mips_defs[] = (1 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M), - .CP0_Config4 = MIPS_CONFIG4, + .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M), .CP0_Config4_rw_bitmask = 0, + .CP0_Config5 = MIPS_CONFIG5, + .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) | + (1 << CP0C5_CV) | (0 << CP0C5_EVA) | + (1 << CP0C5_MSAEn) | (0 << CP0C5_UFR) | + (0 << CP0C5_NFExists), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, |