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| author | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-01-22 18:35:32 +0100 |
|---|---|---|
| committer | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-02-10 16:46:38 +0100 |
| commit | 736d120af4bf5f3e13b2f90c464b3a24847f78f0 (patch) | |
| tree | 01cb88023c2ee383af3dcde2793e756d13b1833e /target-mips/translate_init.c | |
| parent | b4dd99a3636f5a3044dfd9dba7653ca377a9aeba (diff) | |
| download | qemu-736d120af4bf5f3e13b2f90c464b3a24847f78f0.tar.gz | |
target-mips: add user-mode FR switch support for MIPS32r5
Description of UFR feature:
Required in MIPS32r5 if floating point is implemented and user-mode FR
switching is supported. The UFR register allows user-mode to clear StatusFR
by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by
executing a CFC1 to UFR.
helper_ctc1 has been extended with an additional parameter rt to check
requirements for UFR feature.
Definition of mips32r5-generic has been modified to include support for UFR.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 3d4dc88002..29d39e2a39 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -358,18 +358,19 @@ static const mips_def_t mips_defs[] = .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M), .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M), .CP0_Config4_rw_bitmask = 0, - .CP0_Config5 = MIPS_CONFIG5, + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR), .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) | (1 << CP0C5_CV) | (0 << CP0C5_EVA) | - (1 << CP0C5_MSAEn) | (0 << CP0C5_UFR) | + (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) | (0 << CP0C5_NFExists), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x3778FF1F, - .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | - (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), + .CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) | + (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | + (0x93 << FCR0_PRID), .SEGBITS = 32, .PABITS = 32, .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, |