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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-19 16:10:33 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-19 16:10:33 +0000 |
| commit | 8d162c2b68db72623a507069fda0e35ccd1c6b85 (patch) | |
| tree | 3facdd647e9f28271204ce4adfb78886908d32ff /target-mips/translate_init.c | |
| parent | 082c6681b6c4af0035d9dad34a4a784be8c21dbe (diff) | |
| download | qemu-8d162c2b68db72623a507069fda0e35ccd1c6b85.tar.gz | |
Add older 4Km variants.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3708 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index f6bda53fec..6a4c435768 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -101,6 +101,23 @@ static mips_def_t mips_defs[] = .insn_flags = CPU_MIPS32 | ASE_MIPS16, }, { + .name = "4Km", + .CP0_PRid = 0x00018300, + /* Config1 implemented, fixed mapping MMU, + no virtual icache, uncached coherency. */ + .CP0_Config0 = (1 << CP0C0_M) | + (0x3 << CP0C0_MT) | (0x2 << CP0C0_K0), + .CP0_Config1 = MIPS_CONFIG1 | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1258FF17, + .insn_flags = CPU_MIPS32 | ASE_MIPS16, + }, + { .name = "4KEcR1", .CP0_PRid = 0x00018400, .CP0_Config0 = MIPS_CONFIG0, @@ -115,6 +132,23 @@ static mips_def_t mips_defs[] = .insn_flags = CPU_MIPS32 | ASE_MIPS16, }, { + .name = "4KEmR1", + .CP0_PRid = 0x00018500, + /* Config1 implemented, fixed mapping MMU, + no virtual icache, uncached coherency. */ + .CP0_Config0 = (1 << CP0C0_M) | + (0x3 << CP0C0_MT) | (0x2 << CP0C0_K0), + .CP0_Config1 = MIPS_CONFIG1 | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1258FF17, + .insn_flags = CPU_MIPS32 | ASE_MIPS16, + }, + { .name = "4KEc", .CP0_PRid = 0x00019000, .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR), |