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| author | Yongbok Kim <yongbok.kim@imgtec.com> | 2015-06-01 12:13:22 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2015-06-11 10:13:28 +0100 |
| commit | be3a8c53b4f18bcc51a462d977cc61a0f46ebb1c (patch) | |
| tree | 505c13b36909eb0e784269a4d929ad3722fbe6ea /target-mips/translate_init.c | |
| parent | 71c199c81d290b2077ee7cf5400332a342de3a97 (diff) | |
| download | qemu-be3a8c53b4f18bcc51a462d977cc61a0f46ebb1c.tar.gz | |
target-mips: Misaligned memory accesses for R6
Release 6 requires misaligned memory access support for all ordinary memory
access instructions (for example, LW/SW, LWC1/SWC1).
However misaligned support is not provided for certain special memory accesses
such as atomics (for example, LL/SC).
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 8e088c9195..00369f1b01 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -607,7 +607,7 @@ static const mips_def_t mips_defs[] = }, { /* A generic CPU supporting MIPS64 Release 6 ISA. - FIXME: Support IEEE 754-2008 FP and misaligned memory accesses. + FIXME: Support IEEE 754-2008 FP. Eventually this should be replaced by a real CPU model. */ .name = "MIPS64R6-generic", .CP0_PRid = 0x00010000, |