diff options
| author | Leon Alrae <leon.alrae@imgtec.com> | 2015-06-04 17:00:31 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2015-06-11 10:13:29 +0100 |
| commit | ce9782f40ac16660ea9437bfaa2c9c34d5ed8110 (patch) | |
| tree | 359405ef71ce11ab76a77c82450f9af82f0c687e /target-mips/translate_init.c | |
| parent | adc370a48fd26b92188fa4848dfb088578b1936c (diff) | |
| download | qemu-ce9782f40ac16660ea9437bfaa2c9c34d5ed8110.tar.gz | |
target-mips: add ERETNC instruction and Config5.LLB bit
ERETNC is identical to ERET except that an ERETNC will not clear the LLbit
that is set by execution of an LL instruction, and thus when placed between
an LL and SC sequence, will never cause the SC to fail.
Presence of ERETNC is denoted by the Config5.LLB.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 00369f1b01..51e7c986e4 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -403,7 +403,7 @@ static const mips_def_t mips_defs[] = .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP), .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M), .CP0_Config4_rw_bitmask = 0, - .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR), + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR) | (1 << CP0C5_LLB), .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) | (1 << CP0C5_CV) | (0 << CP0C5_EVA) | (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) | @@ -622,6 +622,7 @@ static const mips_def_t mips_defs[] = (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M), .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | (3 << CP0C4_IE) | (1 << CP0C4_M), + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB), .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | (1 << CP0C5_UFE), .CP0_LLAddr_rw_bitmask = 0, |