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| author | Maciej W. Rozycki <macro@codesourcery.com> | 2014-11-04 15:41:20 +0000 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-11-07 14:15:28 +0000 |
| commit | e30614d51780f27c53b196da793c3fb89f1f620f (patch) | |
| tree | 149a5b040050a84557e270da2046955e0ea6b351 /target-mips | |
| parent | 70409e6726aa6ece565c8732f6c5cb5cd5879716 (diff) | |
| download | qemu-e30614d51780f27c53b196da793c3fb89f1f620f.tar.gz | |
mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits
Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit
and the CP0.Config3.DSP bit for the artificial mips32r5-generic and
mips64dspr2 processors. They have the DSPr2 ASE enabled in `insn_flags'
and CPUs that implement that ASE need to have both CP0.Config3.DSP and
CP0.Config3.DSP2P set or software won't detect its presence.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
[leon.alrae@imgtec.com: remove DSP flags from mips32r5-generic]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate_init.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 4dee1caf92..148b394cf0 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -333,7 +333,8 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP), + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | + (0 << CP0C3_VInt), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, @@ -376,7 +377,7 @@ static const mips_def_t mips_defs[] = (0x93 << FCR0_PRID), .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2 | ASE_MSA, + .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA, .mmu_type = MMU_TYPE_R4000, }, #if defined(TARGET_MIPS64) @@ -601,7 +602,8 @@ static const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) | + (1 << CP0C3_DSPP) | (1 << CP0C3_LPA), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 0, .SYNCI_Step = 32, |