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| author | Andreas Färber <afaerber@suse.de> | 2013-09-03 17:38:47 +0200 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2014-03-13 19:52:28 +0100 |
| commit | a47dddd7348d3e75ad650ef5e2ca9c3b13a600ac (patch) | |
| tree | d07f7224ffb752c2bdae0add3ed683ccbb3c7c48 /target-mips | |
| parent | bb0e627a84752707e629fde5534558ac08e7c521 (diff) | |
| download | qemu-a47dddd7348d3e75ad650ef5e2ca9c3b13a600ac.tar.gz | |
exec: Change cpu_abort() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/op_helper.c | 11 | ||||
| -rw-r--r-- | target-mips/translate_init.c | 4 |
2 files changed, 12 insertions, 3 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index de5a22329a..1a785c23d9 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1344,6 +1344,7 @@ void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) { + MIPSCPU *cpu = mips_env_get_cpu(env); uint32_t val, old; uint32_t mask = env->CP0_Status_rw_bitmask; @@ -1365,7 +1366,9 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; - default: cpu_abort(env, "Invalid MMU mode!\n"); break; + default: + cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + break; } } } @@ -1985,6 +1988,8 @@ static void debug_pre_eret(CPUMIPSState *env) static void debug_post_eret(CPUMIPSState *env) { + MIPSCPU *cpu = mips_env_get_cpu(env); + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, env->active_tc.PC, env->CP0_EPC); @@ -1996,7 +2001,9 @@ static void debug_post_eret(CPUMIPSState *env) case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; - default: cpu_abort(env, "Invalid MMU mode!\n"); break; + default: + cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + break; } } } diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 29d39e2a39..a64fd2b530 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -629,6 +629,8 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) static void mmu_init (CPUMIPSState *env, const mips_def_t *def) { + MIPSCPU *cpu = mips_env_get_cpu(env); + env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); switch (def->mmu_type) { @@ -645,7 +647,7 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def) case MMU_TYPE_R6000: case MMU_TYPE_R8000: default: - cpu_abort(env, "MMU type not supported\n"); + cpu_abort(CPU(cpu), "MMU type not supported\n"); } } #endif /* CONFIG_USER_ONLY */ |