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authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2006-05-22 22:03:52 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2006-05-22 22:03:52 +0000
commit9d05095e5fc0609bfb1f46379791abb664680e4b (patch)
tree5cb6579a770c2934d75845a39bf7e921a77f6cfa /target-mips
parentea4e754f5a3c44d82ae7a09daad97e67c4b956a0 (diff)
downloadqemu-9d05095e5fc0609bfb1f46379791abb664680e4b.tar.gz
mips cleanup (Thiemo Seufer)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1934 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/helper.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 752ee72750..d3c64bb7e5 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -219,7 +219,6 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
exception = EXCP_TLBS;
else
exception = EXCP_TLBL;
- error_code = 0;
break;
case -4:
/* TLB match but 'D' bit is cleared */
@@ -350,7 +349,6 @@ void do_interrupt (CPUState *env)
cause = 4;
goto set_EPC;
case EXCP_TLBL:
- case EXCP_TLBF:
cause = 2;
if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
offset = 0x000;