Reworking MIPS interrupt handling, by Aurelien Jarno.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2350 c046a42c-6fe2-441c-8c8c-71466251a162

4 files changed, 18 insertions, 51 deletions

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 8781e3098d..3c99054d6d 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -158,6 +158,7 @@ struct CPUMIPSState {
 #define CP0Ca_IV   23
 #define CP0Ca_WP   22
 #define CP0Ca_IP    8
+#define CP0Ca_IP_mask 0x0000FF00
 #define CP0Ca_EC    2
     target_ulong CP0_EPC;
     int32_t CP0_PRid;
diff --git a/target-mips/exec.h b/target-mips/exec.h
index 3d6bb7d609..15397b6920 100644
--- a/target-mips/exec.h
+++ b/target-mips/exec.h
@@ -164,6 +164,7 @@ uint32_t cpu_mips_get_random (CPUState *env);
 uint32_t cpu_mips_get_count (CPUState *env);
 void cpu_mips_store_count (CPUState *env, uint32_t value);
 void cpu_mips_store_compare (CPUState *env, uint32_t value);
+void cpu_mips_update_irq(CPUState *env);
 void cpu_mips_clock_init (CPUState *env);
 void cpu_mips_tlb_flush (CPUState *env, int flush_global);
 
diff --git a/target-mips/op.c b/target-mips/op.c
index dec9f31ade..9d30d03cd3 100644
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -1357,7 +1357,7 @@ void op_mtc0_compare (void)
 
 void op_mtc0_status (void)
 {
-    uint32_t val, old, mask;
+    uint32_t val, old;
 
     val = (int32_t)T0 & 0xFA78FF01;
     old = env->CP0_Status;
@@ -1374,21 +1374,9 @@ void op_mtc0_status (void)
     else
         env->hflags &= ~MIPS_HFLAG_EXL;
     env->CP0_Status = val;
-    /* If we unmasked an asserted IRQ, raise it */
-    mask = 0x0000FF00;
     if (loglevel & CPU_LOG_TB_IN_ASM)
        CALL_FROM_TB2(do_mtc0_status_debug, old, val);
-    if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) &&
-        !(env->hflags & MIPS_HFLAG_EXL) &&
-        !(env->hflags & MIPS_HFLAG_ERL) &&
-        !(env->hflags & MIPS_HFLAG_DM) &&
-        (env->CP0_Status & env->CP0_Cause & mask)) {
-        env->interrupt_request |= CPU_INTERRUPT_HARD;
-       if (logfile)
-           CALL_FROM_TB0(do_mtc0_status_irqraise_debug);
-    } else if (!(val & (1 << CP0St_IE)) && (old & (1 << CP0St_IE))) {
-        env->interrupt_request &= ~CPU_INTERRUPT_HARD;
-    }
+    CALL_FROM_TB1(cpu_mips_update_irq, env);
     RETURN();
 }
 
@@ -1415,22 +1403,13 @@ void op_mtc0_srsmap (void)
 
 void op_mtc0_cause (void)
 {
-    uint32_t val, old;
+    env->CP0_Cause = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x00C00300);
 
-    val = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x00C00300);
-    old = env->CP0_Cause;
-    env->CP0_Cause = val;
-#if 0
-    {
-        int i, mask;
-       /* Check if we ever asserted a software IRQ */
-        for (i = 0; i < 2; i++) {
-            mask = 0x100 << i;
-            if ((val & mask) & !(old & mask))
-                CALL_FROM_TB1(mips_set_irq, i);
-        }
+    /* Handle the software interrupt as an hardware one, as they
+       are very similar */
+    if (T0 & CP0Ca_IP_mask) {
+        CALL_FROM_TB1(cpu_mips_update_irq, env);
     }
-#endif
     RETURN();
 }
 
@@ -2074,36 +2053,17 @@ void op_pmon (void)
 
 void op_di (void)
 {
-    uint32_t val;
-
     T0 = env->CP0_Status;
-    val = T0 & ~(1 << CP0St_IE);
-    if (val != T0) {
-        env->interrupt_request &= ~CPU_INTERRUPT_HARD;
-        env->CP0_Status = val;
-    }
+    env->CP0_Status = T0 & ~(1 << CP0St_IE);
+    CALL_FROM_TB1(cpu_mips_update_irq, env);
     RETURN();
 }
 
 void op_ei (void)
 {
-    uint32_t val;
-
     T0 = env->CP0_Status;
-    val = T0 | (1 << CP0St_IE);
-    if (val != T0) {
-       const uint32_t mask = 0x0000FF00;
-
-       env->CP0_Status = val;
-       if (!(env->hflags & MIPS_HFLAG_EXL) &&
-           !(env->hflags & MIPS_HFLAG_ERL) &&
-           !(env->hflags & MIPS_HFLAG_DM) &&
-           (env->CP0_Status & env->CP0_Cause & mask)) {
-               env->interrupt_request |= CPU_INTERRUPT_HARD;
-               if (logfile)
-                   CALL_FROM_TB0(do_mtc0_status_irqraise_debug);
-       }
-    }
+    env->CP0_Status = T0 | (1 << CP0St_IE);
+    CALL_FROM_TB1(cpu_mips_update_irq, env);
     RETURN();
 }
 
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index bea5a905e1..9596d04fb6 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -265,6 +265,11 @@ void cpu_mips_store_compare(CPUState *env, uint32_t value)
     cpu_abort(env, "mtc0 compare\n");
 }
 
+void cpu_mips_update_irq(CPUState *env)
+{
+    cpu_abort(env, "mtc0 status / mtc0 cause\n");
+}
+
 void do_mtc0_status_debug(uint32_t old, uint32_t val)
 {
     cpu_abort(env, "mtc0 status debug\n");