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| author | Leon Alrae <leon.alrae@imgtec.com> | 2016-03-15 09:59:35 +0000 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2016-03-30 09:13:59 +0100 |
| commit | bff384a4fbd5d0e86939092e74e766ef0f5f592c (patch) | |
| tree | fc9325844e57fe16f7fd3165c2dd55de6e60f8e6 /target-mips | |
| parent | 67a54961848cd78a82ef23b26a0daf011c1f5d4d (diff) | |
| download | qemu-bff384a4fbd5d0e86939092e74e766ef0f5f592c.tar.gz | |
hw/mips_malta: add CPS to Malta board
If the user specifies smp > 1 and the CPU with CM GCR support, then
create Coherent Processing System (which takes care of instantiating CPUs)
rather than CPUs directly and connect i8259 and cbus to the pins exposed by
CPS. However, there is no GIC yet, thus CPS exposes CPU's IRQ pins so use
the same pin numbers as before.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/cpu.h | 1 | ||||
| -rw-r--r-- | target-mips/translate.c | 10 |
2 files changed, 11 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 55d3224291..63fea676a0 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -760,6 +760,7 @@ MIPSCPU *cpu_mips_init(const char *cpu_model); int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model)) +bool cpu_supports_cps_smp(const char *cpu_model); /* TODO QOM'ify CPU reset and remove */ void cpu_state_reset(CPUMIPSState *s); diff --git a/target-mips/translate.c b/target-mips/translate.c index 8191b9241f..a5b8805f77 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19977,6 +19977,16 @@ MIPSCPU *cpu_mips_init(const char *cpu_model) return cpu; } +bool cpu_supports_cps_smp(const char *cpu_model) +{ + const mips_def_t *def = cpu_mips_find_by_name(cpu_model); + if (!def) { + return false; + } + + return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; +} + void cpu_state_reset(CPUMIPSState *env) { MIPSCPU *cpu = mips_env_get_cpu(env); |