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| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2003-11-23 16:58:08 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2003-11-23 16:58:08 +0000 |
| commit | 28b6751f30603a4c7146282fde9efcf8b5f31f7b (patch) | |
| tree | bced9eef3e217d63465cabdcb28002003d191400 /target-ppc/cpu.h | |
| parent | 79aceca54a8f12a70e23f418ae584e85093c8907 (diff) | |
| download | qemu-28b6751f30603a4c7146282fde9efcf8b5f31f7b.tar.gz | |
suppressed use of gen_multi - use intermediate FT0 register for floats - use T0 temporary for fpscr update - use PARAM1 for spr access - added untested single load/store support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@473 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 12cfc4648c..5b8ea0ad8e 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -172,6 +172,7 @@ typedef struct CPUPPCState { uint32_t exception; /* qemu dedicated */ + uint64_t ft0; /* temporary float register */ int interrupt_request; jmp_buf jmp_env; int exception_index; |