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| author | Cyril Bur <cyril.bur@au1.ibm.com> | 2015-03-02 17:55:38 +1100 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2015-03-09 15:00:07 +0100 |
| commit | 3ba55e399f7637d2b4054bcc30228cd2d0883823 (patch) | |
| tree | 18242d4eac1fe091f14732da0251f187b9718848 /target-ppc/cpu.h | |
| parent | 6494ad9bf4f6e1561f078337d6d82018fd6e7516 (diff) | |
| download | qemu-3ba55e399f7637d2b4054bcc30228cd2d0883823.tar.gz | |
PPC: Introduce the Virtual Time Base (VTB) SPR register
This patch adds basic support for the VTB.
PowerISA:
The Virtual Time Base (VTB) is a 64-bit incrementing counter.
Virtual Time Base increments at the same rate as the Time Base until its value
becomes 0xFFFF_FFFF_FFFF_FFFF (2 64 - 1); at the next increment its value
becomes 0x0000_0000_0000_0000. There is no interrupt or other indication when
this occurs.
The operation of the Virtual Time Base has the following additional
properties.
1. Loading a GPR from the Virtual Time Base has no effect on the accuracy of
the Virtual Time Base.
2. Copying the contents of a GPR to the Virtual Time Base replaces the
contents of the Virtual Time Base with the contents of the GPR.
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index b706b9fdf6..abc3545846 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1624,6 +1624,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_MPC_MD_DBRAM1 (0x32A) #define SPR_RCPU_L2U_RA3 (0x32B) #define SPR_TAR (0x32F) +#define SPR_VTB (0x351) #define SPR_440_INV0 (0x370) #define SPR_440_INV1 (0x371) #define SPR_440_INV2 (0x372) |