diff options
| author | David Gibson <david@gibson.dropbear.id.au> | 2013-04-07 19:08:20 +0000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-04-26 23:02:41 +0200 |
| commit | 702763fa322ea69dde92517735507e0ac3879b5d (patch) | |
| tree | 13dff3f2861c111843819f8c4edcb952054f95e1 /target-ppc/cpu.h | |
| parent | 0cbad81f70546b58f08de3225f1eca7a8b869b09 (diff) | |
| download | qemu-702763fa322ea69dde92517735507e0ac3879b5d.tar.gz | |
target-ppc: Add more stubs for POWER7 PMU registers
In addition to the performance monitor registers found on nearly all
6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and an
extra control register (MMCRA). This patch adds stub support for them to
qemu - the registers won't do anything, but with this change won't cause
illegal instruction traps accessing them. They're also registered with
their ONE_REG ids, so their value will be kept in sync with KVM where
appropriate.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 99ebf7e16a..b8b09b96f0 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1445,6 +1445,7 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp) #define SPR_PERF2 (0x302) #define SPR_RCPU_MI_RBA2 (0x302) #define SPR_MPC_MI_AP (0x302) +#define SPR_MMCRA (0x302) #define SPR_PERF3 (0x303) #define SPR_RCPU_MI_RBA3 (0x303) #define SPR_MPC_MI_EPN (0x303) |