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| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-04 05:25:47 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-04 05:25:47 +0000 |
| commit | f78fb44e825421d386bc44090907d159a04839ef (patch) | |
| tree | 0b9e3c3374bc24fe20700cb0a63cc4086ba8ab60 /target-ppc/cpu.h | |
| parent | 4f821e17574896c046c11bc073c1dc636a6f15d6 (diff) | |
| download | qemu-f78fb44e825421d386bc44090907d159a04839ef.tar.gz | |
ppc: Convert GPR moves to TCG
Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl.
Introduce TCG variables cpu_gpr[0..31].
For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64.
Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers
gen_{load,store}_gpr64. Based on suggestions by Aurelien, Thiemo and Blue.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5153 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 834c08ddd1..c7291ed90c 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -33,17 +33,7 @@ typedef uint64_t ppc_gpr_t; #else /* defined (TARGET_PPC64) */ /* PowerPC 32 definitions */ -#if (HOST_LONG_BITS >= 64) -/* When using 64 bits temporary registers, - * we can use 64 bits GPR with no extra cost - * It's even an optimization as this will prevent - * the compiler to do unuseful masking in the micro-ops. - */ -typedef uint64_t ppc_gpr_t; -#else /* (HOST_LONG_BITS >= 64) */ typedef uint32_t ppc_gpr_t; -#endif /* (HOST_LONG_BITS >= 64) */ - #define TARGET_LONG_BITS 32 #if defined(TARGET_PPCEMB) @@ -541,7 +531,7 @@ struct CPUPPCState { /* First are the most commonly used resources * during translated code execution */ -#if (HOST_LONG_BITS == 32) +#if (TARGET_LONG_BITS > HOST_LONG_BITS) || !defined(TARGET_PPC64) /* temporary fixed-point registers * used to emulate 64 bits registers on 32 bits hosts */ |