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| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-07 20:57:42 +0000 |
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| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-07 20:57:42 +0000 |
| commit | 8eee0af947cafdce5668abb6b7545f3887624ba8 (patch) | |
| tree | 7f48494591bdbc19a040f5412637e80abfc8b251 /target-ppc/cpu.h | |
| parent | e47ce3f2440368a5dac209b910e361658cb601f0 (diff) | |
| download | qemu-8eee0af947cafdce5668abb6b7545f3887624ba8.tar.gz | |
Keep SLB in-CPU
Real 970 CPUs have the SLB not memory backed, but inside the CPU.
This breaks bridge mode for 970 for now, but at least keeps us from
overwriting physical addresses 0x0 - 0x300, rendering our interrupt
handlers useless.
I put in a stub for bridge mode operation that could be enabled
easily, but for now it's safer to leave that off I guess (970fx doesn't
have bridge mode AFAIK).
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6757 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 1c0b753f88..77cf6de71e 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -344,6 +344,12 @@ union ppc_tlb_t { ppcemb_tlb_t tlbe; }; +typedef struct ppc_slb_t ppc_slb_t; +struct ppc_slb_t { + uint64_t tmp64; + uint32_t tmp; +}; + /*****************************************************************************/ /* Machine state register bits definition */ #define MSR_SF 63 /* Sixty-four-bit mode hflags */ @@ -584,6 +590,7 @@ struct CPUPPCState { /* Address space register */ target_ulong asr; /* PowerPC 64 SLB area */ + ppc_slb_t slb[64]; int slb_nr; #endif /* segment registers */ |