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| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-11-27 19:30:47 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-11-27 19:30:47 +0000 |
| commit | 6a6ae23f3c7c80e66e8e900ed9820c7134997a36 (patch) | |
| tree | 1a7419541c2e1c9712d6d6f125867b44ac298d1e /target-ppc/cpu.h | |
| parent | 38d14952014790c8c7f5c098f8048be594a4385d (diff) | |
| download | qemu-6a6ae23f3c7c80e66e8e900ed9820c7134997a36.tar.gz | |
target-ppc: convert SPE load/store to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5804 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 28b9dad715..87d4312e08 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -536,12 +536,6 @@ struct CPUPPCState { #if (TARGET_LONG_BITS > HOST_LONG_BITS) || defined(HOST_I386) target_ulong t2; #endif -#if !defined(TARGET_PPC64) - /* temporary fixed-point registers - * used to emulate 64 bits registers on 32 bits targets - */ - uint64_t t0_64, t1_64, t2_64; -#endif /* general purpose registers */ target_ulong gpr[32]; |