diff options
| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-04 05:26:09 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-04 05:26:09 +0000 |
| commit | bd7d9a6d7bed629cf8363cf8283f1d88946faddd (patch) | |
| tree | e21a7da28b21bc86936ecb216c3a1ed3078ba38d /target-ppc/exec.h | |
| parent | f78fb44e825421d386bc44090907d159a04839ef (diff) | |
| download | qemu-bd7d9a6d7bed629cf8363cf8283f1d88946faddd.tar.gz | |
ppc: cleanup register types
- use target_ulong for gpr and dyngen registers
- remove ppc_gpr_t type
- define 64-bit dyngen registers for GPE register on 32-bit targets
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5154 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/exec.h')
| -rw-r--r-- | target-ppc/exec.h | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/target-ppc/exec.h b/target-ppc/exec.h index 76fdb0b1d6..2b1cfe2586 100644 --- a/target-ppc/exec.h +++ b/target-ppc/exec.h @@ -39,17 +39,16 @@ register struct CPUPPCState *env asm(AREG0); #define T2 (env->t2) #define TDX "%016" PRIx64 #else -register unsigned long T0 asm(AREG1); -register unsigned long T1 asm(AREG2); -register unsigned long T2 asm(AREG3); +register target_ulong T0 asm(AREG1); +register target_ulong T1 asm(AREG2); +register target_ulong T2 asm(AREG3); #define TDX "%016lx" #endif /* We may, sometime, need 64 bits registers on 32 bits targets */ -#if (HOST_LONG_BITS == 32) -/* no registers can be used */ -#define T0_64 (env->t0) -#define T1_64 (env->t1) -#define T2_64 (env->t2) +#if !defined(TARGET_PPC64) +#define T0_64 (env->t0_64) +#define T1_64 (env->t1_64) +#define T2_64 (env->t2_64) #else #define T0_64 T0 #define T1_64 T1 |