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| author | Tom Musta <tommusta@gmail.com> | 2014-01-02 16:21:21 -0600 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-03-05 03:06:28 +0100 |
| commit | ee6e02c0aca020a1934a14c36cff258545dc29b5 (patch) | |
| tree | c113aed0b5871a89f3ff5d6cf2957fd09c55c0e1 /target-ppc/fpu_helper.c | |
| parent | 3c3cbbdc84dbe594b4fa4df52eb8ed6f42d640d8 (diff) | |
| download | qemu-ee6e02c0aca020a1934a14c36cff258545dc29b5.tar.gz | |
target-ppc: Add VSX ISA2.06 xadd/xsub Instructions
This patch adds the floating point addition and subtraction
instructions defined by V2.06 of the PowerPC ISA: xssubdp,
xvsubdp and xvsubsp.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/fpu_helper.c')
| -rw-r--r-- | target-ppc/fpu_helper.c | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index cea94acab6..74c1ce1635 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1758,3 +1758,53 @@ static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) } #define float64_to_float64(x, env) x + + +/* VSX_ADD_SUB - VSX floating point add/subract + * name - instruction mnemonic + * op - operation (add or sub) + * nels - number of elements (1, 2 or 4) + * tp - type (float32 or float64) + * fld - vsr_t field (f32 or f64) + * sfprf - set FPRF + */ +#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf) \ +void helper_##name(CPUPPCState *env, uint32_t opcode) \ +{ \ + ppc_vsr_t xt, xa, xb; \ + int i; \ + \ + getVSR(xA(opcode), &xa, env); \ + getVSR(xB(opcode), &xb, env); \ + getVSR(xT(opcode), &xt, env); \ + helper_reset_fpstatus(env); \ + \ + for (i = 0; i < nels; i++) { \ + float_status tstat = env->fp_status; \ + set_float_exception_flags(0, &tstat); \ + xt.fld[i] = tp##_##op(xa.fld[i], xb.fld[i], &tstat); \ + env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ + \ + if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ + if (tp##_is_infinity(xa.fld[i]) && tp##_is_infinity(xb.fld[i])) {\ + fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \ + } else if (tp##_is_signaling_nan(xa.fld[i]) || \ + tp##_is_signaling_nan(xb.fld[i])) { \ + fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ + } \ + } \ + \ + if (sfprf) { \ + helper_compute_fprf(env, xt.fld[i], sfprf); \ + } \ + } \ + putVSR(xT(opcode), &xt, env); \ + helper_float_check_status(env); \ +} + +VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1) +VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0) +VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0) +VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1) +VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0) +VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0) |