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| author | David Gibson <david@gibson.dropbear.id.au> | 2013-03-12 00:31:47 +0000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-03-22 15:28:53 +0100 |
| commit | f80872e21c07edd06eb343eeeefc8af404b518a6 (patch) | |
| tree | 9334b1d60ca24bfed9d73b0f4b8f072cb20ec25e /target-ppc/mmu-hash64.h | |
| parent | caa597bd9f5439cb16653119f362ad85a9f02b55 (diff) | |
| download | qemu-f80872e21c07edd06eb343eeeefc8af404b518a6.tar.gz | |
mmu-hash64: Implement Virtual Page Class Key Protection
Version 2.06 of the Power architecture describes an additional page
protection mechanism. Each virtual page has a "class" (0-31) recorded in
the PTE. The AMR register contains bits which can prohibit reads and/or
writes on a class by class basis. Interestingly, the AMR is userspace
readable and writable, however user mode writes are masked by the contents
of the UAMOR which is privileged.
This patch implements this protection mechanism, along with the AMR and
UAMOR SPRs. The architecture also specifies a hypervisor-privileged AMOR
register which masks user and supervisor writes to the AMR and UAMOR. We
leave this out for now, since we don't at present model hypervisor mode
correctly in any case.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
[agraf: fix 32-bit hosts]
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/mmu-hash64.h')
| -rw-r--r-- | target-ppc/mmu-hash64.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h index 37ed7ca4ef..55f5a230fd 100644 --- a/target-ppc/mmu-hash64.h +++ b/target-ppc/mmu-hash64.h @@ -69,6 +69,8 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, #define HPTE64_R_C 0x0000000000000080ULL #define HPTE64_R_R 0x0000000000000100ULL #define HPTE64_R_KEY_LO 0x0000000000000e00ULL +#define HPTE64_R_KEY(x) ((((x) & HPTE64_R_KEY_HI) >> 60) | \ + (((x) & HPTE64_R_KEY_LO) >> 9)) #define HPTE64_V_1TB_SEG 0x4000000000000000ULL #define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL |