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| author | Alexander Graf <agraf@suse.de> | 2014-06-04 00:27:31 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:41 +0200 |
| commit | deb6ed13ebfcd6c73548225347c5f63225bb471f (patch) | |
| tree | ecaad95508799ff798d1b748ed5b19dff6f004b4 /target-ppc/mmu_helper.c | |
| parent | f2e2bc9ca06a1c2c6b300c19d4b938c7273a2f76 (diff) | |
| download | qemu-deb6ed13ebfcd6c73548225347c5f63225bb471f.tar.gz | |
PPC: e500: Fix TLB lookup for 32bit CPUs
When we run 32bit guest CPUs (or 32bit guest code on 64bit CPUs) on
qemu-system-ppc64 the TLB lookup will use the full effective address
as pointer.
However, only the first 32bits are valid when MSR.CM = 0. Check for
that condition.
This makes QEMU boot an e500v2 guest with more than 1G of RAM for me.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/mmu_helper.c')
| -rw-r--r-- | target-ppc/mmu_helper.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 1e70536e36..4d6b1e20c0 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -903,6 +903,11 @@ static int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, target_ulong mask; uint32_t tlb_pid; + if (!msr_cm) { + /* In 32bit mode we can only address 32bit EAs */ + address = (uint32_t)address; + } + /* Check valid flag */ if (!(tlb->mas1 & MAS1_VALID)) { return -1; |