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authorAlexander Graf <agraf@suse.de>2012-06-20 21:27:02 +0200
committerAlexander Graf <agraf@suse.de>2012-06-24 01:04:52 +0200
commit2a7a47fc6c19703a849a34243701a09052cb1bc6 (patch)
treeb7206463004047ffd2d1349c0c4c4ea7831d3f7c /target-ppc/mpic_helper.c
parente42a61f185f859246c14445b6e98e195eb3b977b (diff)
downloadqemu-2a7a47fc6c19703a849a34243701a09052cb1bc6.tar.gz
PPC: BookE: Implement EPR SPR
On the e500 series, accessing SPR_EPR magically turns into an access at that CPU's IACK register on the MPIC. Implement that logic to get kernels that make use of that feature work. Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/mpic_helper.c')
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1 files changed, 35 insertions, 0 deletions
diff --git a/target-ppc/mpic_helper.c b/target-ppc/mpic_helper.c
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+/*
+ * PowerPC emulation helpers for QEMU.
+ *
+ * Copyright (c) 2003-2007 Jocelyn Mayer
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "cpu.h"
+#include "helper.h"
+
+/*****************************************************************************/
+/* SPR accesses */
+
+#if !defined(CONFIG_USER_ONLY)
+/*
+ * This is an ugly helper for EPR, which is basically the same as accessing
+ * the IACK (PIAC) register on the MPIC. Because we model the MPIC as a device
+ * that can only talk to the CPU through MMIO, let's access it that way!
+ */
+target_ulong helper_load_epr(CPUPPCState *env)
+{
+ return ldl_phys(env->mpic_cpu_base + 0xA0);
+}
+#endif